Software/Hardware Co-Design of HMM Based Isolated Digit Recognition System

In this paper, the design and implementation results of a system on a chip (SOC) based speech recognition system as software/hardware co-design is presented. The hidden markov model (HMM) is used for the speech recognition. In order to implement this in SOC, the various tasks required are optimally partitioned between hardware and software. The SOC, housed in Altera FPGA boards , has Nios II soft core processor. Custom hardware blocks are developed for computationally intensive blocks such as Viterbi decoder. The preprocessing and training of HMM are implemented in software (using C program). The Viterbi decoding is implemented in hardware as custom block for real time recognition. It is also implemented in software for verification and comparison. It is observed that the sequential hardware implementation of viterbi block is 80 times faster than the software approach using C program with UP3 kit. An over all recognition accuracy of 94.8% is achieved for speaker independent digit recognition for our own database of 6 speakers. Altera’s DE2 board with cyclone II FPGA is used to implement TI46 digit recognition. Since the logical elements in DE2 board is high compared to UP3 kit the viterbi decoding is implemented in parallel for 0-9 digits. Because of this speed of recognition is ‘772’ times faster than software implementation with cyclone II FPGA. And also it is observed that for TI-46 speech database for f1 speaker the recognition accuracy is 87% using LPC as feature extraction technique. Extension of this work for larger vocabulary size and using MFCC as feature extraction is under progress. Index terms – Software/hardware co-design, Custom